The scaling of integrated circuits is a constant effort. With circuits becoming smaller and faster, device current becomes more important. Device current is closely related to transistor gate length, transistor gate capacitance, and carrier mobility. Notably, increasing carrier mobility can improve the device current performance. One technique known to increase carrier mobility is the formation of a stressed silicon channel. Placing silicon under stress can enhance bulk electron and hole mobility.
Stress can be applied to transistor channel regions by forming a stress-inducing contact etch stop layer (CESL) over the transistors. When such a CESL is deposited, due to the lattice spacing mismatch between the CESL and the underlying layer, a stress develops to match the lattice spacing. The stress can have components parallel to the transistor channels and parallel to the transistor width direction. Research has revealed that a CESL that induces a tensile stress field in the channel length direction can improve performance in n-type metal oxide semiconductor (nMOS) transistors, and compressive stress can improve performance in p-type MOS (pMOS) transistors.
High intrinsic stress films commonly used to enhance carrier mobility, such as a CESL, have been found to cause cracks in polysilicon (“poly”) lines forming transistor gates due to mechanical stress. The polysilicon formations are particularly susceptible to cracking in proximity of line junctions, such as T-shaped junctions. Such cracks in the polysilicon formations may increase polysilicon resistance or otherwise deleteriously affect circuit functionality. Accordingly, there exists a need in the art for a method and apparatus that compensates an integrated circuit design for mechanical stress effects, such as those induced by mobility stress engineering.